The present invention relates to a method for manufacturing a semiconductor device and, specifically, it relates to a method for manufacturing a semiconductor device with use of a mold array process (hereafter, also called “MAP”).
Japanese Unexamined Patent Application Publication No. 2002-231741 (Patent Document 1) discloses a method for manufacturing a semiconductor device in which resin molding is performed by injecting a sealing resin into both the cavities of an upper mold and a lower mold.
Japanese Unexamined Patent Application Publication No. 2002-261107 (Patent Document 2) discloses a method for manufacturing a semiconductor device in which resin molding is performed by allowing a molding region over a molding substrate to partially protrude.
Japanese Unexamined Patent Application Publication No. 2003-258158 (Patent Document 3) discloses a method for manufacturing a semiconductor device in which, over a multi-wiring substrate, numbers of warp-preventing holes are provided along the boundary line of unit wiring substrates thereof.
Japanese Unexamined Patent Application Publication No. 2014-204082 (Patent Document 4) discloses a method for manufacturing a semiconductor device in which sealing resin is so injected as to allow a flow of the sealing resin injected from, among a plurality of gates of a molding die, a gate positioned at the end portion to be dispersed.
Japanese Unexamined Patent Application Publication No. 2015-26719 (Patent Document 5) discloses a method for manufacturing a semiconductor device of the MAP type.